# Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication

@article{ONeill2004CoarselyIO, title={Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication}, author={M{\'a}ire O'Neill and Ciaran McIvor and John V. McCanny}, journal={Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)}, year={2004}, pages={185-191} }

A generic coarsely integrated operand scanning (CIOS) architecture that provides high speed Montgomery modular multiplication is presented in This work. The architecture is capable of supporting varying operand sizes. It achieves a throughput of 210 Mbps, 289 Mbps and 334 Mbps for 128-bit, 256-bit and 512-bit operand sizes respectively, when implemented on a Virtex XC2 VP50 FPGA. Throughputs of up to 400 Mbps are achieved if the final subtraction in the Montgomery algorithm is excluded. To the…

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