Clustered VLIW architectures : a quantitative approach

  title={Clustered VLIW architectures : a quantitative approach},
  • Terechko
  • Published 2006
• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version… CONTINUE READING


Publications citing this paper.
Showing 1-9 of 9 extracted citations

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) • 2013
View 1 Excerpt

Scalable register bypassing for FPGA-based processors

Microprocessors and Microsystems - Embedded Hardware Design • 2009
View 1 Excerpt


Publications referenced by this paper.
Showing 1-10 of 24 references

Evaluation of speed and area of clustered VLIW processors

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design • 2005

The TM3270 media-processor

38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05) • 2005

Acht, "Clustered ILP processor and a method for accessing a bus in a clustered

O. M. Pires Dos Reis Moreira, A. Terechko, V.M.G. van
ILP processor", • 2004

Homogeneous multiprocessing for the masses

2nd Workshop onEmbedded Systems for Real-Time Multimedia, 2004. ESTImedia 2004. • 2004

Register file gating to reduce microprocessor power dissipation

A WO2004051449, A. Terechko, M. Garg

Similar Papers

Loading similar papers…