Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance

@article{Underwood2004ClosingTG,
  title={Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance},
  author={K. Underwood and K. Hemmert},
  journal={12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines},
  year={2004},
  pages={219-228}
}
  • K. Underwood, K. Hemmert
  • Published 2004
  • Computer Science
  • 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Field programmable gate arrays (FPGAs) have long been an attractive alternative to microprocessors for computing tasks - as long as floating-point arithmetic is not required. Fueled by the advance of Moore's law, FPGAs are rapidly reaching sufficient densities to enhance peak floating-point performance as well. The question, however, is how much of this peak performance can be sustained. This paper examines three of the basic linear algebra subroutine (BLAS) functions: vector dot product… Expand
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References

SHOWING 1-10 OF 30 REFERENCES
FPGAs vs. CPUs: trends in peak floating-point performance
A re-evaluation of the practicality of floating-point operations on FPGAs
Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
Field programmable gate arrays and floating point arithmetic
Implementation of IEEE single precision floating point addition and multiplication on FPGAs
Tradeoffs of designing floating-point division and square root on Virtex FPGAs
  • Xiaojun Wang, B. Nelson
  • Computer Science
  • 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003.
  • 2003
Floating point unit generation and evaluation for FPGAs
Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques
...
1
2
3
...