Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding

@article{Badaroglu2006ClockskewoptimizationMF,
  title={Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding},
  author={Mustafa Badaroglu and Kris Tiri and Geert Van der Plas and Piet Wambacq and Ingrid Verbauwhede and St{\'e}phane Donnay and Georges G. E. Gielen and Hugo De Man},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2006},
  volume={25},
  pages={1146-1154}
}
In a synchronous clock distribution network with negligible skews, digital circuits switch simultaneously on the clock edge; therefore, they generate a lot of substrate noise due to the resulting sharp peaks on the supply current. A solution is to split a large design in different clock regions and introduce intentional clock skews between them, while taking the timing constraints into account. In this paper, the authors present a complete design flow to optimize the clock tree for less… CONTINUE READING

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