Clock schedule verification under process variations

@article{Chen2004ClockSV,
  title={Clock schedule verification under process variations},
  author={Ruiming Chen and Hai Zhou},
  journal={IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.},
  year={2004},
  pages={619-625}
}
With aggressive scaling down of feature sizes in VLSI fabrication, process variations have become a critical issue in designs, especially for high-performance ICs. Usually having level-sensitive latches for their speed, high-performance IC designs need to verify the clock schedules. With process variations, the verification needs to compute the probability of correct clocking. Because of complex statistical correlations, traditional iterative approaches are difficult to get accurate results… CONTINUE READING
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Principles of Multivariate Analysis

  • W. J. Krzanowski
  • 2000
Highly Influential
5 Excerpts

Path-based statistical timing analysis considering inter- and intra-die correlations

  • A. Agarwal, D. Blaauw, +4 authors R. Panda
  • In ACM Intl. Workshop on Timing Issues in the…
  • 2002
Highly Influential
4 Excerpts

Timing Issues in Sequential Circuits

  • N. V. Shenoy
  • PhD thesis, UC Berkeley,
  • 1993
Highly Influential
5 Excerpts

Tau: Timing analysis under uncertainty

  • A. Bhardwaj, S. B. Vrudhula, D. Blaavw
  • In Proc. Intl. Conf. on Computer- Aided Design,
  • 2003
2 Excerpts

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