• Corpus ID: 17421664

Clock gating on RT-level VHDL

  title={Clock gating on RT-level VHDL},
  author={PeterJ. Schoenmakers and J. F. M. Theeuwen},
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We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transformation for general
R.Witek, \A 200MHz 64b dual-issue CMOS microprocessor,
  • IEEE International Solid-State Circuits Confer- ence,
  • 1992