Clock gating for power optimization in ASIC design cycle theory & practice

@article{Jairam2008ClockGF,
  title={Clock gating for power optimization in ASIC design cycle theory & practice},
  author={Sukumar Jairam and Madhusudan Rao and Jithendra Srinivas and Parimala Vishwanath and H. Udayakumar and Jagdish C. Rao},
  journal={Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)},
  year={2008},
  pages={307-308}
}
In this tutorial we present a comprehensive analysis of the available clock gate (CG) optimization approaches with re-cent innovations available in EDA tools as they have developed in time. Based on these approaches, we propose an integrated and additive design methodology spanning the backend design space. We show that over 30% power savings in dynamic power can be achieved through this methodology subject to application scenarios of the design. 
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