Clock gating and clock enable for FPGA power reduction

  title={Clock gating and clock enable for FPGA power reduction},
  author={Juan P. Oliver and J. Curto and Diego A. Bouvier and Marion Ramos and Eduardo I. Boemo},
  journal={2012 VIII Southern Conference on Programmable Logic},
  • J. Oliver, J. Curto, +2 authors E. Boemo
  • Published 20 March 2012
  • Engineering
  • 2012 VIII Southern Conference on Programmable Logic
This paper presents experimental measurements of power consumption using different techniques to turn off part of a system and switch between active and standby modes. The main ideas analyzed are: clock gating, clock enable, and blocking inputs. The laboratory work is described, including the measurement setups and the benchmark circuits. Quantitative measurements in both a 65 nm CMOS Cyclone III and a 45 nm CMOS Spartan 6 FPGAs are presented. The selected circuits used as benchmarks are… 
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  • Engineering
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