Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)

@article{Pui2017ClockawareUF,
  title={Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)},
  author={Chak-Wa Pui and Gengjie Chen and Yuzhe Ma and Evangeline F. Y. Young and Bei Yu},
  journal={2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  year={2017},
  pages={929-936}
}
As the complexity and scale of circuits keep growing, clocking architectures of FPGAs have become more complex to meet the timing requirement. In this paper, to optimize wirelength and meanwhile meet emerging clocking architectural constraints, we propose several detailed placement techniques, i.e., two-step clock constraint legalization and chain move. After integrating these techniques into our FPGA placement framework, experimental results on ISPD 2017 benchmarks show that our proposed… CONTINUE READING
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An efficient algorithm for the two-dimensional placement problem in electrical circuit layout

  • S. Goto
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