Clock Distribution Networks in Synchronous Digital Integrated Circuits

@inproceedings{Friedman2001ClockDN,
  title={Clock Distribution Networks in Synchronous Digital Integrated Circuits},
  author={Eby G. Friedman},
  year={2001}
}
Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are… CONTINUE READING
Highly Influential
This paper has highly influenced 17 other papers. REVIEW HIGHLY INFLUENTIAL CITATIONS
Highly Cited
This paper has 433 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 283 extracted citations

Implementation of Self Time Adder Using Recursive Approach

Madhukar Anand, A. Saravanan Asst Proff
2016
View 5 Excerpts
Highly Influenced

Bi-dimensional radially-salphasic (standing wave) clock distribution

2014 IEEE 20th International Symposium for Design and Technology in Electronic Packaging (SIITME) • 2014
View 4 Excerpts
Highly Influenced

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2012
View 6 Excerpts
Highly Influenced

Circuit techniques for a 2 GHz AMBA AHB bus

The 3rd International IEEE-NEWCAS Conference, 2005. • 2005
View 4 Excerpts
Highly Influenced

434 Citations

02040'01'04'08'12'16
Citations per Year
Semantic Scholar estimates that this publication has 434 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-10 of 209 references

Elimination of process-dependent clock skew in CMOS VLSI

M. Shoji
IEEE J. Solid-State Circuits , vol. SC-21, pp. 875–880, Oct. 1986. • 1986
View 8 Excerpts
Highly Influenced

Clock generation and distribution for the first IA-64 microprocessor

IEEE Journal of Solid-State Circuits • 2000
View 5 Excerpts
Highly Influenced

Clocking design and analysis for a 600 MHz Alpha microprocessor

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) • 1998
View 7 Excerpts
Highly Influenced

Power dissipation in the clock system of highly pipelined ULSI CMOS circuits

E. De Man, M. Schobinger
inProc. Int. Workshop Low Power Design , Apr. 1994, pp. 133–138. • 1994
View 4 Excerpts
Highly Influenced

Clock Skew Optimization

IEEE Trans. Computers • 1990
View 10 Excerpts
Highly Influenced

Reliable chip design method in high performance CMOS VLSI

M. Hatamian, G. L. Cash
Proc. IEEE Int. Conf. Computer Design , Oct. 1986, pp. 389–392. • 1986
View 7 Excerpts
Highly Influenced

Electrical design of BELLMAC-32A microprocessor

M. Shoji
Proc. IEEE Int. Conf. Circuits and Computers , Sept. 1982, pp. 112–115. • 1982
View 6 Excerpts
Highly Influenced

Pipelining and clocking of high performance synchronous digital systems

E. G. Friedman, J. H. Mulligan
VLSI Signal Processing Technology , M. A. Bayoumi and E. E. Swartzlander Jr., Eds. Norwell, MA: Kluwer, 1994, pp. 97–133. • 1994
View 7 Excerpts
Highly Influenced

A 230 MHz Half Bit Level Pipelined Multiplier using True Single Phase Clocking

The Sixth International Conference on VLSI Design • 1993
View 3 Excerpts
Highly Influenced

Reliable nonzero clock trees using wire width optimization

S. Pullela, N. Menezes, L. T. Pillage
inProc. ACM/IEEE Design Automation Conf. , June 1993, pp. 165–170. • 1993
View 5 Excerpts
Highly Influenced

Similar Papers

Loading similar papers…