Clock Distribution Methodology for PowerPCTM Microprocessors


Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this… (More)
DOI: 10.1023/A:1007991007969


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