Circuit technologies for 16Mb DRAMs

@article{Mano1987CircuitTF,
  title={Circuit technologies for 16Mb DRAMs},
  author={Tsuneo Mano and Tetsuya Matsumura and Junzo Yamada and Junichi Inoue and S. Nakajima and Kazushige Minegishi and Kenji Miura and T. Matsuda and Chisato Hashimoto and Hideo Namatsu},
  journal={1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  year={1987},
  volume={XXX},
  pages={22-23}
}
  • T. Mano, T. Matsumura, +7 authors H. Namatsu
  • Published 1987
  • Computer Science
  • 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
THIS PAPER WILL DESCRIBE circuit technologies not only necessary for submicron ULSl memories, but also for customized ULSIs including RAM blocks. Key circnlts proposed here are an on-chip error checking and correcting (ECC) circuit that induces little access penalty, and sense circuits suitable for fast datasensing at 3.3V operation. A 16Mb CMOS dynamic RAM incorporating a mainsub bitline structure and 4 . 9 p 2 IsolationMerged Vertical Capacitor (IVEC) cells has been designed and fabricated… Expand
A 16mb Dram with an Open Bit-Line Architecture
  • M. Inoue, H. Kotani, +13 authors H. Yamamoto
  • Engineering, Computer Science
  • 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers
  • 1988
TLDR
An open bit-line architecture based on a double layer bit- line and a surrounding Hi-capacitance trench cell that can provide a small geometry memory cell in a high density cell array is developed. Expand
A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register
A single 3.3-V 16-Mbit DRAM with a 135-mm/sup 2/ chip size has been fabricated using a 0.5- mu m twin-well process with double-metal wiring. The array architecture, based on the twisted-bit-lineExpand
An optimized design for high-performance megabit DRAMs
Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. It was found that forExpand
Trends in megabit DRAM circuit design
The state of the art in megabit dynamic random access memory (DRAM) circuit and chip design is reviewed in terms of essential design parameters such as signal-to-noise ratio, power dissipation, andExpand
A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure
Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltageExpand
An experimental 1-Mbit BiCMOS DRAM
Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speedExpand
A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture
TLDR
A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. Expand
A new column redundancy scheme for fast access time of 64-Mb DRAM
A 3.3-V 64-Mbit DRAM is fabricated using 0.4-/spl mu/m CMOS triple poly and double metal process technology. The DRAM implements a new column redundancy scheme called the data line suppression (DLS)Expand
A 50 ns 16 Mb DRAM with a 10 ns data rate
TLDR
A 16-Mb DRAM chip fabricated in a 0.5- mu m CMOS process using silicided polysilicon, double metal, and trench storage is described, providing any-for-any-word-line replacement within a quadrant. Expand
Memory cell and technology issues for 64- and 256-Mbit one-transistor cell MOSD DRAMs
The memory cell and technology requirements and issues for 64- and 256-Mb MOS DRAMs (dynamic random-access memories) based on the charge storage concept (one-transistor cell) are analyzed. ProjectedExpand
...
1
2
3
4
...