Circuit optimization using statistical static timing analysis

  title={Circuit optimization using statistical static timing analysis},
  author={Aseem Agarwal and Kaviraj Chopra and David Blaauw and Vladimir Zolotov},
  journal={Proceedings. 42nd Design Automation Conference, 2005.},
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is difficult to capture the quality of a distribution with a single metric. Hence, we first introduce a new objective function that provides an effective measure for the quality of a delay distribution for both ASIC and high performance designs. We then propose an efficient and exact sensitivity based pruning algorithm based… CONTINUE READING
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A methodology to improve timing yield in the presence of process variations

  • S. Raj, S. Vrudhula, J. Wang
  • 2004
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