Circuit and PD challenges at the 14nm technology node

@inproceedings{Warnock2013CircuitAP,
  title={Circuit and PD challenges at the 14nm technology node},
  author={James D. Warnock},
  booktitle={ISPD},
  year={2013}
}
As traditional CMOS scaling comes to an end, the industry is moving towards new 3D finFET multigate structures as device engineers stand the silicon transistors up on their sides. Digital circuit designers working in the 14nm technology node will face significant new challenges from additional design constraints and new sources of variability associated with this non-planar transistor structure. In addition, computational lithography and the need for double patterning at the 14nm node will… CONTINUE READING