Circuit-Performance Implications for Double-Gate MOSFET Scaling below 25 nm

@inproceedings{Balasubramanian2003CircuitPerformanceIF,
  title={Circuit-Performance Implications for Double-Gate MOSFET Scaling below 25 nm},
  author={Sriram Balasubramanian and Leland Chang and Borivoje Nikolic and Tsu-Jae King},
  year={2003}
}
Circuit-performance implications for double-gate MOSFET scaling in the sub-25 nm gate length regime are investigated. The optimal gate-to-source/drain overlap needed to maximize drive current is found to be different than that needed to minimize FO-4 inverter delay due to parasitic capacitances. It is concluded that the effective channel length must be slightly larger than the physical gate length in order to achieve optimal circuit performance. 
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