• Corpus ID: 17641247

Circuit Optimization and Design Automation Techniques for Low Power CMOS VLSI Design : A Review

@inproceedings{Patil2015CircuitOA,
  title={Circuit Optimization and Design Automation Techniques for Low Power CMOS VLSI Design : A Review},
  author={Shridevi V. Patil},
  year={2015}
}

• Shridevi V. Patil
• Published 2015
• Engineering

Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This paper focuses on circuit optimization and design automation techniques to accomplish this goal. The first part of the paper provides an overview of main sources of leakage current in CMOS transistor. The second part of the paper describes a number of circuit optimization techniques for controlling the standby leakage current. Some leakage current reduction techniques like sleep approach; stack approach, sleepy keeper technique and lector technique are discussed for designing CMOS gates which significantly cuts down the leakage currents. The lector technique with all the advantages like: it does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state as compared to other techniques and it does not affect the dynamic power which is the major limitation with the other leakage reduction techniques, is also discussed in this paper.