Chips go vertical [3D IC interconnection]

@article{Baliga2004ChipsGV,
  title={Chips go vertical [3D IC interconnection]},
  author={Jayant Baliga},
  journal={IEEE Spectrum},
  year={2004},
  volume={41},
  pages={43-47}
}
This article describes 3D ICs. By stacking chips and directly connecting them with vertical wires, chip makers help interconnects keep up with increasing transistor speeds. A 3D IC is a stack of multiple dies with many direct connections tunneling through them, dramatically reducing global interconnect lengths and increasing the number of transistors that are within one clock cycle of each other. The key to the advantage comes from allowing wires to be routed directly between and through the… CONTINUE READING

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