Chip-level simulation for CDM failures in multi-power ICs

@article{Lee2000ChiplevelSF,
  title={Chip-level simulation for CDM failures in multi-power ICs},
  author={Jeasik Lee and Yoonjong Huh and Jau-Wen Chen and Peter Bendix and Sung-Mo Kang},
  journal={Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)},
  year={2000},
  pages={456-464}
}
This paper presents a new chip-level simulation methodology for charged-device model (CDM) failure analysis in multi-power ICs. A circuit model considering reported CDM failures and efficient simulation is proposed and incorporated with the circuit-level ESD simulator, iETSIM. The CDM behaviors in multi-power ICs are analyzed and the vulnerable sites to CDM stress can be predicted by chip-level simulation. Simulation results are verified by CDM testing of a 0.25 /spl mu/m CMOS ASIC and show… CONTINUE READING

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