Chip-level modeling and analysis of electrical masking of soft errors

@article{Kiamehr2013ChiplevelMA,
  title={Chip-level modeling and analysis of electrical masking of soft errors},
  author={Saman Kiamehr and Mojtaba Ebrahimi and Farshad Firouzi and Mehdi Baradaran Tahoori},
  journal={2013 IEEE 31st VLSI Test Symposium (VTS)},
  year={2013},
  pages={1-6}
}
With continuous downscaling of VLSI technologies, logic cells are becoming more susceptible to radiation-induced soft error. To accurately model this at chip-level, the impact of electrical masking should be accurately considered. Moreover, increasing complexity of VLSI chips at nanoscale results in voltage fluctuation across the chip which impacts the electrical masking. In this paper, we present a chip-level electrical masking analysis which accurately considers the impact of voltage… CONTINUE READING

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  • Our analysis shows that neglecting voltage fluctuation in electrical masking can lead up to 152% inaccuracy in the overall soft error rate.

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