Chip-Level ESD-induced noise on internally and externally regulated power supplies

@article{Xiu2017ChipLevelEN,
  title={Chip-Level ESD-induced noise on internally and externally regulated power supplies},
  author={Yang Xiu and Nicholas A. Thomson and Robert Mertens and Collin Reiman and Elyse Rosenbaum},
  journal={2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)},
  year={2017},
  pages={1-10}
}
Power integrity during system-level ESD is studied on two test chips that have different integrated voltage regulator designs. On-chip voltage regulation can provide increased immunity to ESD-induced noise, especially if the internally-generated power supply does not utilize any off-chip decoupling capacitors.