Chemical mechanical polish: The enabling technology

@article{Steigerwald2008ChemicalMP,
  title={Chemical mechanical polish: The enabling technology},
  author={J. Steigerwald},
  journal={2008 IEEE International Electron Devices Meeting},
  year={2008},
  pages={1-4}
}
  • J. Steigerwald
  • Published 2008
  • Materials Science
  • 2008 IEEE International Electron Devices Meeting
Chemical mechanical polishing (CMP) has traditionally been considered an enabling technology. CMP was first used in the early 1990s for BEOL metallization to replanarize the wafer substrate thus enabling advanced lithography which was becoming ever more sensitive to wafer surface topography. Subsequent uses of CMP included density scaling via shallow trench isolation and interconnect formation via copper CMP. As silicon devices scale to 45 nm and beyond however, a large number of new uses of… Expand
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References

SHOWING 1-2 OF 2 REFERENCES
Substituted aluminum metal gate on high-k dielectric for low work-function and Fermi-level pinning free
Substituted aluminum (SA) metal gate on high-K gate dielectric is successfully demonstrated. Full substitution of polysilicon with Al is achieved in Ti/Al/polysilicon/HfAlON gate structure by a lowExpand
within-wafer resistance uniformity 45nm 65nm 0 50 100 RADIUS (mm) center edge 50 100 RADIUS (mm) center edge 150 N or m al iz ed W
  • IEDM Tech Dig.,
  • 2007