Chemical mechanical polish: The enabling technology

  title={Chemical mechanical polish: The enabling technology},
  author={J. Steigerwald},
  journal={2008 IEEE International Electron Devices Meeting},
  • J. Steigerwald
  • Published 2008
  • Materials Science
  • 2008 IEEE International Electron Devices Meeting
Chemical mechanical polishing (CMP) has traditionally been considered an enabling technology. CMP was first used in the early 1990s for BEOL metallization to replanarize the wafer substrate thus enabling advanced lithography which was becoming ever more sensitive to wafer surface topography. Subsequent uses of CMP included density scaling via shallow trench isolation and interconnect formation via copper CMP. As silicon devices scale to 45 nm and beyond however, a large number of new uses of… Expand
Cutting-edge CMP modeling for front-end-of-line (FEOL) and full stack hotspot detection for advanced technologies
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High-k metal gate poly opening polish at 28nm technology polish rate and selective study
  • W. Sie, Y. Liu, +11 authors J. Lin
  • Materials Science
  • Proceedings of International Conference on Planarization/CMP Technology 2014
  • 2014
A robust poly opening polish (POP) CMP for replacement metal gate (RMG) application has been developed to meet the criteria of High-k metal gate (HKMG) devices at 28nm technology node. From theExpand
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High-K/metal gate technology, introduced by Intel, to replace the conventional oxide gate dielectric and polysilicon gate has truly revolutionized transistor technology more than any other changeExpand
Selective Ru ALD as a Catalyst for Sub-Seven-Nanometer Bottom-Up Metal Interconnects.
The approach offers a general strategy for scalable ultrafine 3D nanostructures without the burden of subtractive metal patterning and high cost chemical mechanical planarization processes. Expand
Metal gate etch-back planarization technology
Planarization used in a gate-last CMOS device was successfully developed by particular technologies of SOG two-step plasma etch-back plus one special etch-back step for SOG/SiO2 interface trimming.Expand
A damascene platform for controlled ultra-thin nanowire fabrication.
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Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme
We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of postExpand


Substituted aluminum metal gate on high-k dielectric for low work-function and Fermi-level pinning free
Substituted aluminum (SA) metal gate on high-K gate dielectric is successfully demonstrated. Full substitution of polysilicon with Al is achieved in Ti/Al/polysilicon/HfAlON gate structure by a lowExpand
within-wafer resistance uniformity 45nm 65nm 0 50 100 RADIUS (mm) center edge 50 100 RADIUS (mm) center edge 150 N or m al iz ed W
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