Charge-Mode Parallel Architecture for Vector – Matrix Multiplication

@inproceedings{Genov2001ChargeModePA,
  title={Charge-Mode Parallel Architecture for Vector – Matrix Multiplication},
  author={Roman Genov and Gert Cauwenberghs},
  year={2001}
}
An internally analog, externally digital architecture for parallel vector–matrix multiplication is presented. A threetransistor unit cell combines a single-bit dynamic random-access memory and a charge injection device binary multiplier and analog accumulator. Digital multiplication of variable resolution is obtained with bit-serial inputs and bit-parallel storage of matrix elements, by combining quantized outputs from multiple rows of cells over time. A prototype 512 128 vector–matrix… CONTINUE READING
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