Characterizing Pattern Dependent Delay Effects in DDR Memory Interfaces

@article{Gupta2011CharacterizingPD,
  title={Characterizing Pattern Dependent Delay Effects in DDR Memory Interfaces},
  author={Atul Gupta and Ajay Kumar and Manas Chhabra},
  journal={2011 Asian Test Symposium},
  year={2011},
  pages={425-431}
}
Designing high speed Double Data Rate (DDR) memory interface controller in low cost wire-bond packages is a difficult goal to achieve. The interface is limited at speed because of various factors such as Inter Symbol Interference (ISI), Power Delivery Network (PDN) noise, Cross talk etc. At high speeds like 1Gbps, Pattern dependent effects have a major role to play in DDR link budget analysis. Hence, selecting the right data pattern for DDR interface characterization becomes an important… CONTINUE READING

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