Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

@article{Sun2021CharacterizationOT,
  title={Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection},
  author={H. L. Sun and Datao Gong and W. Zhang and C. Edwards and G. Huang and X Huang and C. Liu and T. Liu and T. Liu and Jamieson Olsen and Q. Sun and J. Wu and J. Ye and L. Zhang},
  journal={Journal of Instrumentation},
  year={2021},
  volume={16}
}
We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16× 16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the… 

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