This paper describes procedures to obtain optimum error models for ADCs using a non-iterative technique. The goal of \phase-plane" compensation for ADCs is to determine the error which is introduced by a converter as a function of the ADC state and the (estimated) slope of the input signal. Past calibration schemes have been frustrated by uncertainties about the input calibration signal. In this paper, the error characteristic is expressed as a linear combination of a set of basis functions, which is then optimized to minimize the harmonic distortion in the output sample sequence. Degradation in performance due to inaccurate estimates of the input signal is avoided. The theories developed in this paper are applied to an 8-bit ADC sampling at 204.8 MSPS. Experimental results show that dynamic range performance can be improved by as much as 12 dB over the Nyquist band. A further interesting result is that an error function measured for one ADC is found to work equally well for another ADC taken from the same production run. The errors determined are thus found to be unique to the ADC design and production, and not to the test and representation methods. It is believed that this is the rst time that results of this nature have been reported in the literature.