Characterization and modeling of hysteresis phenomena in high K dielectrics

@article{Leroux2004CharacterizationAM,
  title={Characterization and modeling of hysteresis phenomena in high K dielectrics},
  author={Charles Leroux and J. Mitard and G{\'e}rard Ghibaudo and Xavier Garros and Gilles Reimbold and B. Guillaumor and François Martin},
  journal={IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.},
  year={2004},
  pages={737-740}
}
An original technique for the dynamic analysis of Id(Vg) hysteresis on high K stacks is proposed, allowing the characterization of Vt shift transients at short times. The experimental results demonstrate that trapping/de-trapping mechanism by tunneling from the substrate must be considered. Furthermore, a new model based on a trap-like approach is successfully developed to interpret the dependence of hysteresis phenomena with high k gate stack architecture. 
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