Challenges in the Design of High-Speed Clock and Data Recovery Circuits

  • Published 2002

Abstract

This article describes the challenges in the design of monolithic clock and data recovery circuits used in high-speed transceivers. Following an overview of general issues, the task of phase detection for random data is addressed. Next, Hogge, Alexander, and half-rate phase detectors are introduced and their trade-offs outlined. Finally, a number of clock… (More)

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