Challenges and Limitations of Low Power Techniques: Low Power Methodologies in Analog and Digital Circuits

@inproceedings{Vandana2016ChallengesAL,
  title={Challenges and Limitations of Low Power Techniques: Low Power Methodologies in Analog and Digital Circuits},
  author={Balakrishnan Vandana and B. Shivalal Patro},
  year={2016}
}
In contemporary world the technology has kept its vast identity in developing ultra NANO devices to give up the compact device utilities, in VLSI, Metal Oxide Semiconductor device plays an key role in power dissipation product, in terms of MOS theory characteristics it is predefined that a MOS transistor can conduct easily with low voltage which gives low power but in DSM technology there is a likelihood to achieve ultra low power, so this can be achieved due to the rapid shrinking of gate… CONTINUE READING

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