This paper describes a number of techniques that use perfect reconstruction (PR) non-maximally decimated filter banks (NMDFBs) to implement variable bandwidth filters. These processes entail three tightly coupled tasks. The first task uses an M-path analysis filter bank to partition the full bandwidth input time series into a set of M reduced bandwidth, reduced sample rate, intermediate time series. The second task selects the subset of the M channel time series whose contiguous spectra spans the design bandwidth of the digital filter. The third task uses the M-path PR synthesis bank to assemble the desired output time series from the subset of selected channel time series. The first benefit of this process is that the computational workload of the cascade analysis-synthesis filter bank filter implementation is typically an order of magnitude below that of the tapped delay line, direct implementation, of the same filter. A second benefit is that a high data rate input time series is partitioned into a set of multiple, reduced sample rate, intermediate time series processed by reduced speed parallel arithmetic processors. This process enables simple, reduced cost, processing of input signals with GHz sample rates.