Capacitive Coupling Mitigation for TSV-based 3D ICs

Abstract

TSV-to-TSV capacitive coupling has large disruptive effects on timing requirements of the circuit. The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a TSV using circuit-level model is presented in this article. Two coding approaches are proposed to mitigate capacitive parasitic effects by adjusting the current flow pattern for any given n×n mesh of TSV arrangement to reduce the number of 8C/7C parasitic capacitance. The experimental results proves the efficacy of the proposed coding methods.

DOI: 10.1109/VTS.2015.7116279

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Cite this paper

@inproceedings{Eghbal2015CapacitiveCM, title={Capacitive Coupling Mitigation for TSV-based 3D ICs}, author={Ashkan Eghbal and Pooria M. Yaghini and Nader Bagherzadeh}, booktitle={VTS}, year={2015} }