Capability Hardware Enhanced RISC Instructions : CHERI Instruction-Set Architecture ( Version 6 )

@inproceedings{Watson2014CapabilityHE,
  title={Capability Hardware Enhanced RISC Instructions : CHERI Instruction-Set Architecture ( Version 6 )},
  author={Robert N. M. Watson and Peter G. Neumann and Jonathan Woodruff and Michael Roe and Jonathan Anderson and John Baldwin and David Chisnall and Brooks Davis and Alexandre Joannou and Ben Laurie and Simon W. Moore and Steven J. Murdoch and Robert Norton and Hongyan Xia},
  year={2014}
}
This technical report describes CHERI ISAv3, the third version of the Capability Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA) being developed by SRI International and the University of Cambridge. This design captures four years of research, development, refinement, formal analysis, and testing, and is a substantial enhancement to the ISA version described in UCAM-CL-TR-850. Key improvements lie in tighter C-language integration, and more mature support for… CONTINUE READING
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