A Congestion Driven Placement Algorithm for FPGA Synthesis
Engineering change order (ECO)s for FPGA-based designs often require design changes late in the design process in order to correct functional, timing, and/or technological problems. Typically, after an ECO process a small portion of the circuit netlist is changed. To take advantage of the enormous resources and time already spent on place and route flow, it is desirable to maintain similar post-routing delay characteristics to the pre-ECO stage to avoid further expensive design iterations. Most FPGA tools use the variance to their advantage to explore the solution space in the design optimization phase. FPGA companies can afford to run multiple passes and just retain the best solution. The embedded systems companies cannot afford multiple pass compile times especially in ECO situations. Note that the variance reduction technique proposed in this paper is applicable only in the ECO situations and not during design optimization phase where variance plays an advantageous role. Predictability is not just unique to ECO, but success of an ECO is highly dependent on predictability and that’s where the proposed approach plays a crucial role. The ECO process may change a small subset of the circuit netlist, which may result in a minor variation in the instance list order seen by the packer. Most packing heuristics, including fast greedy heuristics as well as relatively slower nongreedy heuristics, process the input netlist in a certain order and have varying degrees of dependence on the initial instance order. Even a slight variation may result in a substantially different packing and the subsequent placement and routing results may also change. In the worst case, the postrouting delay may fail timing constraints and require inexpensive design iteration. In this paper, we propose a fast canonical ordering technique that either guarantees a unique instance order if the ECO process caused a change in the initial instance order or minimizes the perturbation to the instance order as seen by the packer stage from any significant ECO-induced change to the initial instance order. This helps in isolating the postpacker place and route flow from netlist changes and drastically reduces the variance in post routing delay. Experimental results demonstrate zero variance against random shuffling of instances before the packer stage (to simulate an ECO scenario). Experimental results for other non-functional or slight functional modifications to the input netlist show greatly reduced post-routing delay variance.