Calculation of Minimum Number of Registers in 2-D Discrete Wavelet Transforms Using Lapped Block Processing

@inproceedings{Denk1994CalculationOM,
  title={Calculation of Minimum Number of Registers in 2-D Discrete Wavelet Transforms Using Lapped Block Processing},
  author={Tracy C. Denk and Keshab K. Parhi},
  booktitle={ISCAS},
  year={1994}
}
This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format conveters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately ( N 1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform. 
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