Calculating the FHT in hardware

@article{Erickson1992CalculatingTF,
  title={Calculating the FHT in hardware},
  author={Adam C. Erickson and B. Fagin},
  journal={IEEE Trans. Signal Process.},
  year={1992},
  volume={40},
  pages={1341-1353}
}
A parallel, pipelined architecture for calculating the fast Hartley transform (FHT) is discussed. Hardware implementation of the FHT introduces two challenges: retrograde indexing and data scaling. A novel addressing scheme that permits the fast computation of FHT butterflies is proposed, and a hardware implementation of conditional block floating point scaling that reduces error due to data growth with little extra cost is described. Simulations reveal a processor capable of transforming a 1 K… Expand
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