Cache timing side-channel vulnerability checking with computation tree logic

@inproceedings{Deng2018CacheTS,
  title={Cache timing side-channel vulnerability checking with computation tree logic},
  author={Shuwen Deng and Wenjie Xiong and Jakub Szefer},
  booktitle={HASP@ISCA},
  year={2018}
}
Caches are one of the key features of modern processors as they help to improve memory access timing through caching recently used data. However, due to the timing differences between cache hits and misses, numerous timing side-channels have been discovered and exploited in the past. In this paper, Computation Tree Logic is used to model execution paths of the processor cache logic, and to derive formulas for paths that can lead to timing side-channel vulnerabilities. In total, 28 types of… CONTINUE READING

Similar Papers

Citations

Publications citing this paper.
SHOWING 1-2 OF 2 CITATIONS

Analysis of Secure Caches and Timing-Based Side-Channel Attacks

  • IACR Cryptology ePrint Archive
  • 2019
VIEW 3 EXCERPTS
CITES METHODS
HIGHLY INFLUENCED

Secure TLBs

VIEW 1 EXCERPT
CITES RESULTS