Cache-based Computer Systems

@article{Kaplan1973CachebasedCS,
  title={Cache-based Computer Systems},
  author={Kenneth R. Kaplan and Robert O. Winder},
  journal={Computer},
  year={1973},
  volume={6},
  pages={30-36}
}
A cache-based computer system employs a fast, small memory -the " cache" - interposed between the usual processor and main memory. At any given time the cache contains as much as possible the instructions and data the processor needs; as new information is needed it is brought from main memory to cache, displacing old information. The processor tends to operate with a memory of cache speed but with main memory cost-per-bit. This configuration has analogies with other systems employing memory… 
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82 Citations
Highly Influential Citations
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Background Citations
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Methods Citations
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Results Citations
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82 Citations

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Citation Type

Cache memory performance in a unix enviroment
TLDR
The intent is to credibly quantify the performance implications of parameter selection in a manner which emphasizes implementation tradeoffs using address reference traces obtained from typical multitasking UNIX workloads to research cache memory performance.
The Memory System of a High-Performance Personal Computer
The memory system of the Dorado, a compact high- performance personal computer, has very high I/O bandwidth, a large paged virtual memory, a cache, and heavily pipelined control; this paper discusses…
Using cache memory to reduce processor-memory traffic
TLDR
It is demonstrated that a cache exploiting primarily temporal locality (look-behind) can indeed reduce traffic to memory greatly, and introduce an elegant solution to the cache coherency problem.
Cache system design in the tightly coupled multiprocessor system
TLDR
System requirements in the multiprocessor environment as well as the cost-performance trade-offs of the cache system design are given in detail and the possibility of sharing the Cache system hardware with other multiprocessioning facilities (such as dynamic address translation, storage protection, locks, serialization, and the system clocks) is discussed.
Cache memory systems for multiprocessor architecture
TLDR
By appropriate cache system design, adequate memory system speed can be achieved to keep the processors busy and smaller cache memories are required for dedicated processors than for standard processors.
Lockup-free instruction fetch/prefetch cache organization
TLDR
A cache organization is presented that essentially eliminates a penalty on subsequent cache references following a cache miss and has been incorporated in a cache/memory interface subsystem design, and the design has been implemented and prototyped.
Lockup-free instruction fetch/prefetch cache organization
TLDR
A cache organization is presented that essentially eliminates a penalty on subsequent cache references following a cache miss and has been incorporated in a cache/memory interface subsystem design, and the design has been implemented and prototyped.
Stack-Based Single-Pass Cache Simulation
TLDR
This chapter and the following chapter address the problem of simulating cache-based memory systems, which optimally requires measurement of the performance of a large number of cache designs.
An efficient flexible buffered memory system
TLDR
A flexible low cost multiclass memory system has been evaluated and constructed to accommodate memory sizes from 128 000 to 4 000 000 ten-bit bytes to achieve an efficient directory and update list by a high-speed segmented memory using memory cells with half the access time of the buffer memory.
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
TLDR
An approximate model is developed to estimate the processor utilization and the speed-up improvement provided by the caches, and it assumes a two-dimensional organization, previously studied under random and word access.
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References

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