Cache Sensitive Modulo Scheduling

@inproceedings{Snchez1997CacheSM,
  title={Cache Sensitive Modulo Scheduling},
  author={F. Jes{\'u}s S{\'a}nchez and Antonio Gonz{\'a}lez},
  booktitle={MICRO},
  year={1997}
}
This paper focus on the interaction between software prefetching (both binding and nonbinding) and software pipelining for VLIW machines. First, it is shown that evaluating software pipelined schedules without considering memory effects can be rather inaccurate due to stalls caused by dependences with memory instructions (even if a lockup-free cache is considered). It is also shown that the penalty of the stalls is in general higher than the effect of spill code. Second, we show that in general… CONTINUE READING
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