Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor

Abstract

The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to increase the compute density of high-volume commodity 2P/4P blade servers while operating within the same power envelope as earlier-generation AMD Opteron processors. A key enabling feature… (More)
DOI: 10.1109/MM.2010.31

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@article{Conway2010CacheHA, title={Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor}, author={Pat Conway and Nathan Kalyanasundharam and Gregg Donley and Kevin Lepak and Bill Hughes}, journal={IEEE Micro}, year={2010}, volume={30} }