CSER: BISER-based concurrent soft-error resilience

@article{Wang2010CSERBC,
  title={CSER: BISER-based concurrent soft-error resilience},
  author={Laung-Terng Wang and Nur A. Touba and Zhigang Jiang and Shianling Wu and Jiun-Lang Huang and Chien-Mo James Li},
  journal={2010 28th VLSI Test Symposium (VTS)},
  year={2010},
  pages={153-158}
}
This paper presents a concurrent soft-error resilience (CSER) scheme with features that aid manufacturing test, online debug, and defect tolerance. The proposed CSER scheme is based on the built-in soft-error resilience (BISER) technique [4]. A BISER cell is redesigned into various robust CSER cells that provide slow-speed snapshot, manufacturing test, slow-speed signature analysis, and defect tolerance capabilities. The cell-level area, power, and performance overhead of the robust CSER cells… CONTINUE READING

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