CPL-Adiabatic Gated logic (CPLAG) XOR gate


In this paper authors have investigated the appropriateness of adiabatic circuit design techniques aiming to reduce the power dissipation by the VLSI circuits. Authors have implemented/proposed CPL based Adiabatic Gated (CPLAG) XOR gate which can be synchronized with the reference clock signal. The implemented CPLAG XOR gate is analyzed for different voltage levels for the capacitance involved with the power dissipation. The circuit is also analyzed for different temperature gradients for its functional and operational robustness in different operating conditions. The circuit operation is also tested to resetting the output node and associated power data. The implemented CPLAG based XOR gate has minimum dissipated power of 3.52&#x00D7;10<sup>-11</sup>W at 1v and maximum power of 6.10&#x00D7;10<sup>-10</sup>W at 5v. The power clock path offers maximum capacitance 1.40&#x00D7;10<sup>10</sup>F contributing 22% of the total circuit capacitance. From the power delay product it is found that the circuit best performs at 2v across different temperature ranges. After rigorous testing the circuit is found to be functionally successful.

DOI: 10.1109/ICACCI.2013.6637236

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@article{Sharma2013CPLAdiabaticGL, title={CPL-Adiabatic Gated logic (CPLAG) XOR gate}, author={Manoj K Sharma and Arti Noor}, journal={2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)}, year={2013}, pages={575-579} }