CORDIC Designs for Fixed Angle of Rotation

  title={CORDIC Designs for Fixed Angle of Rotation},
  author={Pramod Kumar Meher and Sang Yoon Park},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  • P. MeherS. Park
  • Published 1 February 2013
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rotation of vectors through fixed and known angles has wide applications in robotics, digital signal processing, graphics, games, and animation. But, we do not find any optimized coordinate rotation digital computer (CORDIC) design for vector-rotation through specific angles. Therefore, in this paper, we present optimization schemes and CORDIC circuits for fixed and known rotations with different levels of accuracy. For reducing the area- and time-complexities, we have proposed a hardwired pre… 


CORDIC means coordinate rotation digital computer. Rotation of vectors through fixed and known angles has wide applications in robotics, digital signal processing, graphics, games, and animation .It

Area and time efficient hardwired pre -shifted bi-rotation CORDIC design

Synthesized the proposed CORDIC cells by Synopsys Design Compiler using TSMC 90-NM library, and shown that the proposed designs offer higher throughput, less latency and less area-delay product than the reference CORDic design for fixed and known angles of rotation.

Implementation of Optimized CORDIC Designs

This paper proposes optimization schemes and CORDIC circuits for fixed and known rotations for rotating vectors through specific angles and an argument reduction technique to map larger angle to an angle less than 45 is discussed.

FPGA Implementation of Sine and Cosine Value Generators using CORDIC Design for Fixed Angle Rotation

This paper has proposed a simplified pipelined CORDIC architecture model by writing appropriate programs in VHDL for calculating sine and cosine values of an angle with fixed number of iterations that helps in achieving reduced On-chip area and power consumption compared to previous reference conventional CORDic architecture models.

Reconfigurable Design of Pipelined CORDIC Processor for Digital Sine-Cosine

The design of an application-specific CORDIC processor in circular rotation mode gives high system throughput due to pipelined architecture by reducing latency in each individual pipelining stage and the computed quantization error is minimized using a required number of iterations.

Design of Cascaded CORDIC Based on Precise Analysis of Critical Path

A fine-grained critical path analysis of the cascaded CORDIC in terms of bit-level delay is presented and an algorithm for determining the required number of pipeline stages and locations of the pipeline registers in order to meet the time constraint in a particular application is proposed.

Selective Rotation-Based CORDIC Architecture for High-Speed Applications

The conventional CORDIC algorithm is optimized using selective rotation (SR) techniques which employ rotation selection algorithm (RSA) for faster convergence and a coarse LUT (Look up Table) is incorporated in the design to obtain coarse values which are fine-tuned using SR CordIC stages.

An efficient folded pipelined architecture for Fast Fourier Transform using Cordic algorithm

A highly efficient pipelined folded FFT architecture for 8 point R2 FFT is presented here and shows efficiency both in speed and area consumption.

Area-energy efficient CORDICs using new elementary-angle-set and base-2 exponent expansions scheme

The proposed CORDICs adopt a new Elementary-Angle-Set, based on which the elementary angle composition of input angle can be directly determined without angle recoding, and the Angle-Set ensures the directions of vector micro-rotation are deterministic anti-clockwise in first quadrant.

A CORDIC-friendly FFT architecture

This paper introduces a restructure of the butterflies of the radix-2 FFT to be more CORDIC friendly, which achieves superior signal to quantization noise ratio (SQNR), and leads to an improvement in latency or a reduction in the total area.



Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture

A novel Coordinate Rotation Digital Computer (CORDIC) rotator algorithm that converges to the final target angle by adaptively executing appropriate iteration steps while keeping the scale factor virtually constant and completely predictable is proposed.

Para-CORDIC: parallel CORDIC rotation algorithm

The parallel COrdinate Rotation DIgital Computer (CORDIC) rotation algorithm in circular and hyperbolic coordinate is proposed and the critical path delay is reduced since the concurrently predicted rotations can be combined using multioperand carry-save addition structures.

Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications

  • Chih-Hsiu LinA. Wu
  • Computer Science
    IEEE Transactions on Circuits and Systems I: Regular Papers
  • 2005
This paper proposes a new vector rotational scheme called mixed-scaling-rotation coordinate rotational digital computer (MSR-CORDIC) algorithm, which can eliminate the overhead of the scaling operations that are inevitable in existing CORDIC algorithms; hence, it can significantly reduce the total iteration number so as to improve the speed performance.

An Angle Recoding Method for CORDIC Algorithm Implementation

A greedy algorithm which takes only O(n/sup 2/) operations is developed to perform CORDIC angle recoding, and it is proven that this algorithm is able to reduce the total number of required elementary rotation angles by at least 50% without affecting the computational accuracy.

The CORDIC Trigonometric Computing Technique

The trigonometric algorithms used in this computer and the instrumentation of these algorithms are discussed in this paper.

A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding (BAR)

It is proved that for each of the linear, circular, and hyperbolic CORDIC rotations, the use of BAR guarantees more than 50% reduction of elementary CORDic rotations provided the scaling factor needs not be kept constant.

A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes

The proposed EEAS-based CORDIC algorithm can improve the overall SQNR performance by up to 25 dB compared with previous works, and a novel scaling operation is suggested, called Extended Type-II (ET-II) scaling operation, which results in much smaller quantization error than conventional Type-I scaling operation in the numerical approximation of scaling factor.

50 Years of CORDIC: Algorithms, Architectures, and Applications

A brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications is presented.

High-throughput CORDIC-based geometry operations for 3D computer graphics

This paper presents the formulation of representative 3D computer graphics operations in terms of CORDIC-type primitives, and briefly outlines a stream processor based on CORDic-type modules to efficiently implement these graphic operations.

Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation

Two area-efficient algorithms and their architectures based on CORDIC that eliminate ROM and requires only low-complexity barrel shifters and are applicable to the entire range of angles are presented.