COOL interconnect low power interconnection technology for scalable 3D LSI design

@article{Chacin2011COOLIL,
  title={COOL interconnect low power interconnection technology for scalable 3D LSI design},
  author={Marco Chacin and Hiroyuki Uchida and Michiya Hagimoto and Takashi Miyazaki and Takeshi Ohkawa and Rimon Ikeno and Yukoh Matsumoto and Fumito Imura and Motohiro Suzuki and Katsuya Kikuchi and Hiroshi Nakagawa and Masahiro Aoyagi},
  journal={2011 IEEE Cool Chips XIV},
  year={2011},
  pages={1-3}
}
3D multi-chip stacking is a promising technology poised to help combat the “memory wall” and the “power wall” in future multi-core processors. However, as technology scales and the chip sizes increase due to the number of transistors, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. In this article, we introduce a TSV-based ultra-wide inter-chip connection technology that enables systems to have lower power consumption, higher… CONTINUE READING

Citations

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Cool Interconnect: A 1024-bit Wide Bus for Chip-to-Chip Communications in 3-D Integrated Circuits

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  • 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
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Investigation of effects of die thinning on central TSV bus driver thermal performance

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Method for back-annotating per-transistor power values onto 3DIC layouts to enable detailed thermal analysis

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