# COMPARISON OF SCALABLE MONTGOMERY MODULAR MULTIPLICATION IMPLEMENTATIONS EMBEDDED IN RECONFIGURABLE HARDWARE

@inproceedings{Fischer2006COMPARISONOS, title={COMPARISON OF SCALABLE MONTGOMERY MODULAR MULTIPLICATION IMPLEMENTATIONS EMBEDDED IN RECONFIGURABLE HARDWARE}, author={Viktor Fischer}, year={2006} }

SUMMARY This paper presents a comparison of possible approaches for an efficient implementation of Multiple-word radix-2 Montgomery Modular Multiplication (MM) on modern Field Programmable Gate Arrays (FPGAs. [... ] Key Method The first of analyzed implementations uses a data path based on traditionally used redundant carry-save adders, the second one exploits, in scalable designs not yet applied, standard carry-propagate adders with fast carry chain logic. Expand

## 2 Citations

Maximizing the Efficiency using Montgomery Multipliers on FPGA in RSA Cryptography for Wireless Sensor Networks

- Computer Science, Mathematics
- 2017

The architecture and modeling of RSA public key encryption/ decryption systems are presented and the implementation of RSA encryption/decryption algorithm on FPGA using 128 bits data and key size with RSACIPHER128 gives good result with 50% less utilization of hardware.

Proto-cluster: A Parallel Computer Architecture Based on Prototyping Boards

- Computer Science2018 16th International Conference on Emerging eLearning Technologies and Applications (ICETA)
- 2018

The solution to design a low-cost parallel environment, a proto-cluster to support computational problem-solving by applying principles of task decomposition is presented.

## References

SHOWING 1-10 OF 29 REFERENCES

Comparison of Two Implementations of Scalable Montgomery Coprocessor Embedded in Reconfigurable Hardware

- Computer Science
- 2004

It is shown that carrysave adder is not an optimal building block for constrained scalable MM coprocessor in modern FPLDs.

Montgomery modular exponentiation on reconfigurable hardware

- Computer Science, MathematicsProceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)
- 1999

This contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs) and shows that it is possible to implement modular exponentiation at secure bit lengths on a single commercially available FPGA.

Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic

- Computer ScienceFPGA '02
- 2002

Some new architectures are presented, including a pipelined architecture exploiting the maximum carry chain length of the FPGA which is used to implement the modular exponentiation operation required for RSA encryption and decryption.

Scalable RSA Processor in Reconfigurable Hardware-a SoC Building Block

- Computer Science
- 2001

A scalable programmable RSA cryptographic processor implemented as IP core in Field Programmable Devices (FPD) that can be used in more complex cryptographic chip using both symmetrical and asymmetrical algorithms.

Implementation of Scalable Montgomery Multiplication Coprocessor in Altera Reconfigurable Hardware

- Computer Science
- 2001

* Technical University of Košice, Department of Electronics and Multimedia Communications, Park Komenského 13, 04120 Košice, Slovak Republic, E-mail: Milos.Drutarovsky@tuke.sk, Tel: ++421-55-6024169…

A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm

- Computer ScienceIEEE Trans. Computers
- 2003

A word-based version of MM is presented and used to explain the main concepts in the hardware design and gives enough freedom to select the word size and the degree of parallelism to be used, according to the available area and/or desired performance.

A Scalable Architecture for Montgomery Multiplication

- Computer ScienceCHES
- 1999

The general view of the new architecture is described, hardware organization for its parallel computation is analyzed, and design tradeoffs which are useful to identify the best hardware configuration are discussed.

Montgomery's Multiplication Technique: How to Make It Smaller and Faster

- Computer ScienceCHES
- 1999

It is concluded that a linear, pipelined implementation of the modular multiplication algorithm may be part of best policy in thwarting differential power attacks against RSA.

Apex ii programmable logic device family data sheet

- Computer Science
- 2002

Features... ■ Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration – MultiCoreTM architecture integrating look-up table (LUT) logic,…

Hardware Implementation of Montgomery's Modular Multiplication Algorithm

- Computer Science, MathematicsIEEE Trans. Computers
- 1993

Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985), showing that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures.