CMOS wavelet compression imager architecture

@article{Olyaei2005CMOSWC,
  title={CMOS wavelet compression imager architecture},
  author={Ashkan Olyaei and Roman Genov},
  journal={2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications},
  year={2005},
  pages={104-107}
}
The CMOS imager architecture implements /spl Delta//spl Sigma/-modulated Haar wavelet image compression on the focal plane in real time. The active pixel array is integrated with a bank of column-parallel first-order incremental over-sampling analog-to-digital converters (ADCs). Each ADC performs column-wise distributed focal-plane sampling and concurrent signed weighted average quantization, realizing a one-dimensional spatial Haar wavelet transform. A digital delay and adder loop performs… CONTINUE READING

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