CMOS technology scaling, 0.1 /spl mu/m and beyond

  • Behroz Davari
  • Published 1996 in
    International Electron Devices Meeting. Technical…


A projection of CMOS technology scaling and the expected performance, density, and power improvements are presented. Technology for scaling to sub-0.1 /spl mu/m effective channel length (L/sub eff/) is discussed, and the key barriers are examined. It is shown that device speed enhancement of about 3X, circuit density improvement of 8X, and 20-40X… (More)


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@article{Davari1996CMOSTS, title={CMOS technology scaling, 0.1 /spl mu/m and beyond}, author={Behroz Davari}, journal={International Electron Devices Meeting. Technical Digest}, year={1996}, pages={555-558} }