CMOS shallow trench isolation x-stress effect on channel width for 130nm technology

@article{Tan2006CMOSST,
  title={CMOS shallow trench isolation x-stress effect on channel width for 130nm technology},
  author={Philip Beow Yew Tan and A. Kordesch and Othman Sidek},
  journal={2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings},
  year={2006},
  pages={478-480}
}
In this paper, we investigated the compressive mechanical STI x-stress (in the direction of channel length) on channel width. When the channel width becomes narrower, the compressive STI y-stress effect become more severe and causes STI x-stress has lower effect on NMOS Idsat but has higher effect on PMOS Idsat. This means that the amount of NMOS Idsat decrement due to x-stress become less but the amount of PMOS Idsat increment due to x-stress become higher when y-stress increases (narrower… CONTINUE READING