CMOS design near the limit of scaling

@inproceedings{Taur2002CMOSDN,
  title={CMOS design near the limit of scaling},
  author={Yuan Taur},
  year={2002}
}
Beginning with a brief review of CMOS scaling trends from 1 µm to 0.1 µm, this paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length. Both the standby power and the active power of a processor chip will increase precipitously below the 0.1-µm or 100-nm technology generation. To… CONTINUE READING

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