CMOS analog front-end IC for EEG applications with high powerline interference rejection

@article{Costa2018CMOSAF,
  title={CMOS analog front-end IC for EEG applications with high powerline interference rejection},
  author={Jorge Augusto Costa and Tales Cleber Pimenta},
  journal={2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS)},
  year={2018},
  pages={1-4}
}
This paper presents a CMOS low-power analog front-end (AFE) circuit for EEG applications and research beyond the standard clinical relevant frequency range. The instrumentation amplifier (IA) is developed using operational transconductance amplifiers (OTA) as resistive load for gain adjustment. The lowpass notch filter (LPNF) has a capacitor programmable circuit that, due to the powerline interefence, selects between cutting 50 or 60 Hz signals. The AFE subcircuit consumes only 750 nW with 1 V… CONTINUE READING

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