CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out

@article{Gurrieri2008CMOSIS,
  title={CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out},
  author={T. Gurrieri and M. S. Carroll and M. P. Lilly and J. E. Levy},
  journal={2008 8th IEEE Conference on Nanotechnology},
  year={2008},
  pages={609-612}
}
Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a… CONTINUE READING
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