CMOS Digital Pixel for Binary Morphological Edge Segmentation

Abstract

A digital pixel for binary morphological image processing is presented. The pixel is designed to be integrated into a vision chip with parallel architecture, in order to compute edge segmentation. The pixel contains 11 transistors working with analog signal and 20 transistor working with digital signal; pixel layout size is 115.2 mum times 89.4 mum; fill factor is 1.85%; 1.2 mum CMOS standard technology from AMI is used for prototyping; random noise is 2.7 mV; peak analog output signal to noise ratio is 44 dB; optical dynamic range is 53 dB; dark current is 11 mV/s; processing time is 3.5 ms; maximum power dissipation is 264 muW.

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Cite this paper

@article{GarciaLamont2007CMOSDP, title={CMOS Digital Pixel for Binary Morphological Edge Segmentation}, author={J. Garcia-Lamont and E. N. Vazquez-Acosta and Guillermo S{\'a}nchez-D{\'i}az and J. L. Gonzalez-Vidal}, journal={Electronics, Robotics and Automotive Mechanics Conference (CERMA 2007)}, year={2007}, pages={266-270} }